APP NOTE: Give your voltage regulator the margin it deserves

Texas instruments has an app note and video explaining how to make a programmable output power supply using a typical LDO voltage regulator and a DAC. This is the technique we used for the Bus Pirate Ultra power supply to get 0.8 to 5volts output, and it works a treat!

Consider the currents going in and out of the VFB node shown in Figure 3, which is connected to the ADJ pin of the LDO. Almost no current flows in or out the device through the ADJ pin (on the order of 0.01µA). As I previously mentioned, the output voltage of the LDO is always produced such that the voltage at the ADJ pin – and therefore the VFB node – is equal to the LDO’s internal reference voltage. Thus, the current through R2 is constant. It follows that any sourcing or sinking of current by the DAC through R3 is reflected as a proportional voltage increase or decrease at VOUT to compensate for the changing current that must flow through R1.

Linear Nixie tube HAT for the Raspberry Pi

Mark Smith has been working on a HAT for the Raspberry Pi that can drive two IN-9 or IN-13 linear Nixie tubes:

This project as described in www.surfncircuits.com came about because I needed a retro looking linear meter for my espresso maker water tank. I’m always running out of water in my espresso maker, and a cool display letting me know how much water is left and to let me know when to fill it up is definitely needed. In this project, I’ll create a HAT for the Raspberry Pi that can drive two IN-9 or IN-13 linear Nixie tubes. While I’m using this HAT as a single water meter display, this same linear display would be great for showing temperature, bar graphs, audio VU meters, even surf heights by days of the week. The Nixie Tube Power Supply, designed in an earlier blog will work perfectly to drive up to four of the IN-13 Nixie tubes or one IN-9 Nixie tube.

More details on surfncircuits blog and the GitHub repository here.

Bus Pirate Ultra display board v1d

Sorry for the poor image export. What have they done to Eagle?

The LCD carrier board for Bus Pirate prototype “Ultra” v1d went out today. This update matches the form factor of Ultra v1d (in progress) and has several minor changes:

  • Uses 10 pin 0.5mm flexible PCB connector, wired to the main board with a 1:N connection. This connector is much smaller and thinner than the 1.25mm connector on v1b, it reduces the space needed between the display board and the main board.
  • Flipped LCD orientation 180 degrees so font data can be written into bounding boxes in a more natural “left-to-right” orientation, eliminating the need to precalculate the text end point and write characters in reverse sequence
  • Nudged the display towards the IO header. We’ll experiment with some buttons in the remaining available space
  • Decoupling capacitors on LCD power pins

The 2 inch 240*320 IPS LCD display we’re been testing has a very pleasing pixel density, but we’re also itching to try the bigger 2.8 inch version. Next week we’ll send out a prototype carrier board for the bigger display, as well as some Bus Plug breakout boards.

Cheaper yet powerful camera solutions

The Landingfield writes:

It’s been a while since my last blog post. During this past year, I’ve built a few other cameras yet released on this blog. In the meantime, I have been looking into options to make this work available to fellow amateur astronomers as a viable product. One major blocker here is the cost. FPGAs are expensive devices due to two factors: 1. They are less produced compared to ASIC and still uses state of art silicon process. 2. Massive area dedicated to routing and configuration logic. Let’s look at a simple comparison. The MicroZed board I’m using cost $200 with dual Cortex-A9 core clocking at 666MHz. This contrasts with quad core Ras Pi 3B clocking at doubling frequency. And it only cost $30.

See the full post on The Landingfield blog.

BUS PIRATE: ADS7042 Analog to Digital Converter chip

Source: ADS7041 datasheet

In Bus Pirate prototype “Ultra” v1b we added analog voltage measurement to all the IO pins using a 74HCT4051 8:1 analog multiplexer and an op-amp. In the next revision we’re moving control of as many peripherals as possible into the FPGA. The FPGA doesn’t have an Analog to Digital Converter feature, so we need to add an external ADC chip.

We chose ADS7041/ADS7042 10/12 bit ADCs capable of 1MSPS with an SPI interface. The 12 bit version is $1.75 in 100s, the 10 bit version is slightly cheaper ($1.06). The 10 and 12 bit versions are pin-compatible. We’ll try both and decide later what works best.

There are much cheaper SPI ADCs, but for around a dollar this chip does 1 MSPS with a simple 3 wire interface. That’s the same top speed as the DSO Nano v3, so we can record samples in the two SRAMs and have a very minimal oscilloscope function on any IO pin.

Source: ADS7041 datasheet

The interface is read-only and doesn’t have any registers to configure, that’ll keep it simple to work with from the FPGA. Each conversion begins with two clock ticks, then the 10 or 12 bit reading follows. The maximum clock speed is 14MHz to achieve 1MSPS, easy to do with the FPGA.

This post is just a quick followup to yesterday’s look at three Digital to Analog Converter chips.

BUS PIRATE: three inexpensive SPI Digital to Analog Converters

Source: Microchip MCP4902 datasheet

As much as possible, we’d like to move control of all the Bus Pirate peripheral hardware to the FPGA. Then everything can be controlled through the state machine command pipeline. In Ultra v1c we moved analog voltage measurement to the FPGA by adding an SPI ADC. In a future revision it would make sense to move a few other things to the FPGA:

  • Pull-up resistor control
  • Programmable output power supply enable
  • Programmable output power supply margining (using a DAC)
  • v1d stuff not yet announced

For debugging and self-testing we need to keep some redundant connections to the MCU as well, but primary control should be through the FPGA.

We had a look at a few chips that could replace the Digital to Analog Converter in the MCU, here’s a few inexpensive options we considered:

MCP4902 8bit dual DAC TSSOP14

Source: Microchip MCP4902 datasheet

MCP4902 seems to be a classic Microchip part, available at Mouser for $0.99 in 100s. However, the smallest package size is TSSOP14 and a quick check of SZLCSC shows they only have the SOIC version with 17 pieces in stock. That’s not a great sign.

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Source: Microchip MCP4902 datasheet

Each update of a DAC channel uses a 16bit command, maximum speed is 20MHz.

MCP48FVB02 8bit dual DAC MSOP10

Source: Microchip MCP48FVB02 datasheet

MCP48FVB02 appears to be a part Microchip acquired when they bought Micrel. It comes in an MSOP10 package which is an improvement over the MCP4902. It’s a bit cheaper at $0.90 for 100pcs at Mouser. It’s not stocked at SZLCSZ, which is a huge warning sign. Microchip Direct is really good about delivering parts in China if need be, but they can only deliver 1200 today and new stock won’t be available until February (three and a half months away).

Source: Microchip MCP48FVB02 datasheet

MCP48FVB02 uses a 24bit command to update each DAC, which is a full byte longer than the MCP4092. Both the MCP4092 and MCP48FVB02 operate at maximum write speeds of 20MHz, so the MCP48FVB02 will have a significantly slower maximum update rate.

DAC082S085CIMM/DAC084S085CIMM 8bit dual/quad DAC MSOP10

Source: DAC082S085 datasheet

Here’s where it gets a bit interesting. DAC082S085CIMM is a dual 8 bit DAC from Texas Instruments, available for $1.24 in 100s at Mouser. SZLCSC only has 8 in stock for around $2 in 100s (13.20RMB). Low stock is bad news, and a higher RMB price than USD price that points to a limited stock or specialty chip to avoid (i.e. not something with high demand in China).

However, the DAC084S085CIMM is similar but has 4 DACs. We could use the extra DACs to add more programmable output power supplies, or add a simple analog signal generator on a few of the IO pins. It’s available at Mouser for $1.58 in 100s, and at SZLCSC for $1.15 (8.68RMB) with 1700 available and 1300 shipped in the last month. That’s several good signs: it’s cheaper than the 2 DAC version ($2 vs $1.15), RMB price is cheaper than USD price, and there is a fair amount of stock and turnover at SZLCSC which means it’s probably being used in production somewhere. This seems like a good candidate.

Just to further verify, there are 50K in stock at the TI store, and 20K in stock at Digikey for a slightly higher price.

Source: DAC082S085 datasheet

Commands are 16bits, but where it really shines is the 40MHz maximum update speed. Twice as many DACs, and twice twice as fast as the Microchip DACs.

This is by no accounts an exhaustive list, but after looking at stock on Mouser, Digikey, and SZLCSC these were the best options close to $1. Did we miss your favorite DAC?

4 Port high power USB hub

Dilshan Jayakody has published a new build:

In the last couple of years, I tried several powered USB hubs to drive some development boards and USB peripherals. Most of the USB hubs which we can find in the local market are unreliable or not designed to drive more than 500mA of a load.
After having a few bad experiences with powered USB hubs, I decided to build a USB hub by myself. I specifically design this hub to drive USB powered development boards and experimental peripherals.

See the full post on his blog.

BUS PIRATE: pipelined and non-pipelined commands

Bus Pirate prototype Ultra v1b uses an FPGA to process commands sent through a FIFO buffer to a state machine. Pipelined commands can be loaded into the FIFO and executed by the state machine with per-clock repeatability. Non-pipelined commands halt the state machine while the MCU takes over to perform the command, the delay is unpredictable and depends on many factors such as USB operations the MCU may be servicing.

These commands are currently pipelined and handled in the FPGA by the state machine:

  • Delays (ms, us)
  • Bus reads
  • Bus writes
  • Pin read/write/direction

These commands can be pipelined, but are currently handled in registers:

  • PWM
  • Frequency measurement

These commands will be pipelined in v1c and later:

  • ADC reads (on any pin, Vout)

These commands could be pipelined with some hardware updates:

  • Pull-up resistors toggle
  • Power supply enable
  • Power supply margining (by adding an external DAC)

These commands cannot be pipelined because they happen outside the FPGA:

  • Mode change (reloads the FPGA)
  • Reset
  • Jump to bootloader
  • Self-test (involves tests on the MCU and FPGA)

There are also mode macros to consider, which probably need to be a combination of pipelined commands and non-pipelined commands. This week we’ll choose an external DAC and add it to the board.

BUS PIRATE: first test of Ultra v1b with SPI EEPROM

Bus Pirate prototype “Ultra” v1b successfully wrote to and read back from a 25LC020A SPI EEPROM chip. The image shows the Bus Pirate reading 8 bytes of 0x02 from the EEPROM at address 0x00, and the bus activity can be verified on the logic analyzer graph. Still a long way to go, but it’s nice to have everything working.

Tomorrow we’ll finish the major SPI commands and general purpose mode features like analog measurement and manipulation of the auxiliary pins. As always, you can follow our latest progress in the forum.

Evolution of the Bus Pirate, the road to Ultra

Sjaak @ SMDprutser has been instrumental in pushing the Bus Pirate firmware and hardware ever forward. Check out his history of the evolution Bus Pirate “Ultra” for some great background:

Unfortunately we run more or less into the same issues as we had with the Microchip controller: USB need regularly attention, which interferes with our interaction on the protocols, so we end up with stalls. Another big issue was that the peripherals were designed with moving data efficiently around and not in an educational way (as the BusPirate is ment to be). For example the I2C is nicely designed for reading memories or writing displays fast, but we need to know beforehand which byte is last. As we only can send a stop byte one or two bytes in advance of the stop bit. The design of the BusPirate menu system doesn’t cope with this properly (without major redesign).

As always, you can join Sjaak and Ian for development fun in the forum.