The primary reason we ordered these now is to get a feel for how the pinout color scheme works in practice before we commit to it permanently.
The leads are 30cm long, which seems a bit unwieldy in real life. The next version will be a few centimeters shorter.
One end is terminated with 1 pin female “DuPont” connectors. These are easy to use with breakout boards and bread boards that have 2.54mm header pins. We’ll need to choose a nice probe hook and mating crimp eventually.
While the wire quality is fine (top), it’s a bit stiff and we’d prefer something really nice for the final cable. The Saleae Logic cable (bottom) has really amazing tangle free wire with great flexibility. We took the Saleae cable to a bunch of wire manufacturers in Shenzhen, but none of them had anything close in terms of quality and flexibility. Our search will continue.
In addition to the 2 inch IPS LCD we’re been using with the Bus Pirate prototype “Ultra”, we’re also sending off a PCB for a larger 2.8 inch display. Both panels are 240*320 pixels, so the larger version probably won’t look quite as stunning as the smaller display with high pixel density. If it does pass muster, a capacitive touch screen controller option is available that might be an interesting addition.
A differential pin pair can be used as a comparator to create a basic ADC. This app note shows how to design a low speed (1 KHz) and “high” speed (50 Khz) ADC technique using only FPGA pins, a resistor and a capacitor. Regardless of whether we ever use this technique, it is illuminating to understand how SAR and Delta Sigma ADCs are constructed:
A simple Analog to Digital Converter can be constructed by adding a small RC circuit to an LVDS input on an FPGA or CPLD…. The LVDS input will act as a simple analog comparator and will output a digital ‘1’ if the Analog Input voltage is higher than the voltage from the RC network. By changing the voltage on the input to the RC circuit, the LVDS comparator can be used to analyze the Analog Input voltage to create an accurate digital representation… A low frequency signal can be processed using a simple Successive Approximation Register… A higher frequency implementation…can be implemented using a Delta Sigma Modulator function, which consists of a sampling register and a Cascade Integrated Comb (CIC) Filter.
Texas instruments has an app note and video explaining how to make a programmable output power supply using a typical LDO voltage regulator and a DAC. This is the technique we used for the Bus Pirate Ultra power supply to get 0.8 to 5volts output, and it works a treat!
Consider the currents going in and out of the VFB node shown in Figure 3, which is connected to the ADJ pin of the LDO. Almost no current flows in or out the device through the ADJ pin (on the order of 0.01µA). As I previously mentioned, the output voltage of the LDO is always produced such that the voltage at the ADJ pin – and therefore the VFB node – is equal to the LDO’s internal reference voltage. Thus, the current through R2 is constant. It follows that any sourcing or sinking of current by the DAC through R3 is reflected as a proportional voltage increase or decrease at VOUT to compensate for the changing current that must flow through R1.
Uses 10 pin 0.5mm flexible PCB connector, wired to the main board with a 1:N connection. This connector is much smaller and thinner than the 1.25mm connector on v1b, it reduces the space needed between the display board and the main board.
Flipped LCD orientation 180 degrees so font data can be written into bounding boxes in a more natural “left-to-right” orientation, eliminating the need to precalculate the text end point and write characters in reverse sequence
Nudged the display towards the IO header. We’ll experiment with some buttons in the remaining available space
Decoupling capacitors on LCD power pins
The 2 inch 240*320 IPS LCD display we’re been testing has a very pleasing pixel density, but we’re also itching to try the bigger 2.8 inch version. Next week we’ll send out a prototype carrier board for the bigger display, as well as some Bus Plug breakout boards.
We chose ADS7041/ADS7042 10/12 bit ADCs capable of 1MSPS with an SPI interface. The 12 bit version is $1.75 in 100s, the 10 bit version is slightly cheaper ($1.06). The 10 and 12 bit versions are pin-compatible. We’ll try both and decide later what works best.
There are much cheaper SPI ADCs, but for around a dollar this chip does 1 MSPS with a simple 3 wire interface. That’s the same top speed as the DSO Nano v3, so we can record samples in the two SRAMs and have a very minimal oscilloscope function on any IO pin.
The interface is read-only and doesn’t have any registers to configure, that’ll keep it simple to work with from the FPGA. Each conversion begins with two clock ticks, then the 10 or 12 bit reading follows. The maximum clock speed is 14MHz to achieve 1MSPS, easy to do with the FPGA.
As much as possible, we’d like to move control of all the Bus Pirate peripheral hardware to the FPGA. Then everything can be controlled through the state machine command pipeline. In Ultra v1c we moved analog voltage measurement to the FPGA by adding an SPI ADC. In a future revision it would make sense to move a few other things to the FPGA:
Pull-up resistor control
Programmable output power supply enable
Programmable output power supply margining (using a DAC)
v1d stuff not yet announced
For debugging and self-testing we need to keep some redundant connections to the MCU as well, but primary control should be through the FPGA.
We had a look at a few chips that could replace the Digital to Analog Converter in the MCU, here’s a few inexpensive options we considered:
MCP4902 8bit dual DAC TSSOP14
MCP4902 seems to be a classic Microchip part, available at Mouser for $0.99 in 100s. However, the smallest package size is TSSOP14 and a quick check of SZLCSC shows they only have the SOIC version with 17 pieces in stock. That’s not a great sign.
Each update of a DAC channel uses a 16bit command, maximum speed is 20MHz.
MCP48FVB02 8bit dual DAC MSOP10
MCP48FVB02 appears to be a part Microchip acquired when they bought Micrel. It comes in an MSOP10 package which is an improvement over the MCP4902. It’s a bit cheaper at $0.90 for 100pcs at Mouser. It’s not stocked at SZLCSZ, which is a huge warning sign. Microchip Direct is really good about delivering parts in China if need be, but they can only deliver 1200 today and new stock won’t be available until February (three and a half months away).
MCP48FVB02 uses a 24bit command to update each DAC, which is a full byte longer than the MCP4092. Both the MCP4092 and MCP48FVB02 operate at maximum write speeds of 20MHz, so the MCP48FVB02 will have a significantly slower maximum update rate.
Here’s where it gets a bit interesting. DAC082S085CIMM is a dual 8 bit DAC from Texas Instruments, available for $1.24 in 100s at Mouser. SZLCSC only has 8 in stock for around $2 in 100s (13.20RMB). Low stock is bad news, and a higher RMB price than USD price that points to a limited stock or specialty chip to avoid (i.e. not something with high demand in China).
However, the DAC084S085CIMM is similar but has 4 DACs. We could use the extra DACs to add more programmable output power supplies, or add a simple analog signal generator on a few of the IO pins. It’s available at Mouser for $1.58 in 100s, and at SZLCSC for $1.15 (8.68RMB) with 1700 available and 1300 shipped in the last month. That’s several good signs: it’s cheaper than the 2 DAC version ($2 vs $1.15), RMB price is cheaper than USD price, and there is a fair amount of stock and turnover at SZLCSC which means it’s probably being used in production somewhere. This seems like a good candidate.
Just to further verify, there are 50K in stock at the TI store, and 20K in stock at Digikey for a slightly higher price.
Commands are 16bits, but where it really shines is the 40MHz maximum update speed. Twice as many DACs, and twice twice as fast as the Microchip DACs.
This is by no accounts an exhaustive list, but after looking at stock on Mouser, Digikey, and SZLCSC these were the best options close to $1. Did we miss your favorite DAC?
Bus Pirate prototype Ultra v1b uses an FPGA to process commands sent through a FIFO buffer to a state machine. Pipelined commands can be loaded into the FIFO and executed by the state machine with per-clock repeatability. Non-pipelined commands halt the state machine while the MCU takes over to perform the command, the delay is unpredictable and depends on many factors such as USB operations the MCU may be servicing.
These commands are currently pipelined and handled in the FPGA by the state machine:
Delays (ms, us)
These commands can be pipelined, but are currently handled in registers:
These commands will be pipelined in v1c and later:
ADC reads (on any pin, Vout)
These commands could be pipelined with some hardware updates:
Pull-up resistors toggle
Power supply enable
Power supply margining (by adding an external DAC)
These commands cannot be pipelined because they happen outside the FPGA:
Mode change (reloads the FPGA)
Jump to bootloader
Self-test (involves tests on the MCU and FPGA)
There are also mode macros to consider, which probably need to be a combination of pipelined commands and non-pipelined commands. This week we’ll choose an external DAC and add it to the board.
Bus Pirate prototype “Ultra” v1b successfully wrote to and read back from a 25LC020A SPI EEPROM chip. The image shows the Bus Pirate reading 8 bytes of 0x02 from the EEPROM at address 0x00, and the bus activity can be verified on the logic analyzer graph. Still a long way to go, but it’s nice to have everything working.
Tomorrow we’ll finish the major SPI commands and general purpose mode features like analog measurement and manipulation of the auxiliary pins. As always, you can follow our latest progress in the forum.
Unfortunately we run more or less into the same issues as we had with the Microchip controller: USB need regularly attention, which interferes with our interaction on the protocols, so we end up with stalls. Another big issue was that the peripherals were designed with moving data efficiently around and not in an educational way (as the BusPirate is ment to be). For example the I2C is nicely designed for reading memories or writing displays fast, but we need to know beforehand which byte is last. As we only can send a stop byte one or two bytes in advance of the stop bit. The design of the BusPirate menu system doesn’t cope with this properly (without major redesign).
As always, you can join Sjaak and Ian for development fun in the forum.