FPGA-based disk controller for Apple II


Steve Chamberlin over at Big Mess o’Wires has been working on an FPGA-based disk controller for Apple II, which he call Yellowstone:

Apple II disk controller cards are weird, there are a crazy number of different types, and many are rare and expensive. Can an FPGA-based solution save the day for retro collectors? You bet! Nearly all the existing disk controllers connect the same 8-bit bus to the same 19-pin disk interface, so a universal clone is merely a question of replacing the vintage 80s guts of the card with a modern reprogrammable FPGA. This hypothetical universal controller card could connect to almost any Apple II disk drive, or a Floppy Emu. Here’s my first attempt.

More details at Big Mess o’ Wires homepage.

BML USB 3.0 FPGA interface over PMOD


An open-source-hardware USB 3.0 to FPGA PMOD interface design from Black Mesa Labs:

Black Mesa Labs is presenting an open-source-hardware USB 3.0 to FPGA PMOD interface design.  First off, please lower your expectations. USB 3.0 physical layer is capable of 5 Gbps, or 640 MBytes/Sec. This project can’t provide that to your FPGA over 2 PMOD connectors – not even close. It does substantially improve PC to FPGA bandwidth however, 30x for Writes and 100x for Reads compared to a standard FTDI cable based on the FT232 ( ala RS232 like UART interface at 921,600 baud ). A standard FTDI cable is $20 and the FT600 chip is less than $10, so BML deemed it a project worth pursuing.

More details at Black Mesa Labs homepage.

Via the contact form.

BML HDMI video for FPGAs over PMOD

BML HDMIvideoforFPGAs over PMOD

Here are two open-source-hardware HDMI  video boards for adding digital video to FPGA platforms with standard PMOD connectors from Black Mesa Labs:

The BML 3bit HDMI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 using a 40 MHz dot clock. The TI TFP410 is very versatile in the resolutions it can generate and is really just limited by the clock that the FPGA can provide and the data rates the PMOD connectors are capable of.

More details at Black Mesa Labs homepage.

App note: Choose the right power supply for your FPGA


Designing a power supply for FPGA includes multiple voltage, ripple management and power sequencing, here’s an app note from Maxim Integrated. Link here (PDF)

Field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) require 3 to 15, or even more, voltage rails. The logic fabric is usually at the latest process technology node that determines the core supply voltage. Configuration, housekeeping circuitry, various I/Os, serializer/deserializer (SerDes) transceivers, clock managers, and other functions all have differing requirements for voltage rails, sequencing/tracking, and voltage ripple limits. An engineer must consider all of these issues when designing a power supply for an FPGA.

App note: Clearing Xilinx FPGA configuration to allow boundary scan testing

Another application note from XJTAG on preparing Xilinx FPGA for proper boundary scan testing. Link here

When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing boundary scan testing to occur without any problems.

A second issue that can affect boundary scan testing with FPGAs is that they contain pull resistors. Depending on the design, these may be enabled when the FPGA is unconfigured as well as when it is configured. If these internal resistors are enabled on nets that contain pull resistors mounted on the board, two potential problems can occur:

1. If the internal resistor and external resistor pull in opposite directions, the boundary scan tests may not be able to test the external pull resistor if it is weaker than the internal pull resistor.
2. If the internal and external resistors pull in the same direction, a fault with the external resistor may not be detected because the internal resistor may mask the fault.

By setting the correct configuration options it is possible to disable these internal pull resistors when generating a ‘blank’ FPGA image.

App note: Active capacitor discharge circuit considerations for FPGAs


Power down sequencing and discharging on FPGAs app note from Diodes Incorporated. Link here (PDF)

FPGA’s need the different power rails to be powered up and down in a defined sequence. For power down, each sequenced rail needs to be fully off before the next rail is turned off. With large high speed and high functionality FPGA’s, the power rails have large bulk capacitors to be discharged quickly and safely within a total time of 100ms and up to 10 rails each to be discharged within 10ms.

This application note shows a methodology and considerations for safe open ended shutdown to be controlled by a power sequencing circuit and using correctly chosen MOSFET to discharge the capacitor bank.

A FPGA controlled RGB LED MATRIX for Incredible Effects – the Hardware

Boris Landoni from Open Electronics writes:

In this post you will find  the description of a graphic display that uses a modular solution based on dot matrix blocks (in which each dot is a RGB LED), that are driven – via a specific bus – by a very powerful control board, that is entirely programmable and capable of managing even very fast animations, thanks to the FPGA it is supplied with. Yes, the key factor is the Spartan-6 Field Programmable Gate Array by Xilinx, that is able to execute programs at very high speed, thanks to its parallel processing capability (multi-thread); the model that has been used in the project was chosen because it represents the most performing FPGA available on the market as a TQFP package, therefore it may still be soldered by means of the traditional tools.

More details at Open Electronics’ Open Source Projects page.

FPGA Computer Covers A to Z

[F4HDK] calls his new computer A2Z because he built everything from scratch (literally, from A to Z). Well, strictly speaking, he did start with an FPGA, but you have to have some foundation. The core CPU is a 16-bit RISC processor with a 24-bit address bus and a 128-word cache. The computer sports 2 megabytes of RAM, a boot ROM, a VGA port and keyboard, and some other useful I/O. The CPU development uses Verilog.

Software-wise, the computer has a simple operating system, a filesystem, and basic programs like a text editor and an image viewer. Development software includes an assembler and a compiler for a BASIC-like language that resides on the PC. You can also run an emulator to experiment with A2Z without hardware. You can see a “car game” running on A2Z in the video below. You can also see videos of some other applications.

The game shows off the VGA double buffering. Many FPGA developers develop “clone” CPUs so they can leverage development tools and software. A2Z is a unique design and we’ve rarely seen a custom CPU that has such a wide range of tools and applications.

We’ve talked about the difficulties of developing your own infrastructure around a custom CPU before. We’ve also covered some of our CPUs (don’t forget part two).

Filed under: computer hacks, FPGA

Retro ZX Spectrum Lives a Spartan Existence

FPGAs (like Xilinx’s Spartan series) are great building blocks. They often remind us of the 100-in-1 electronic kits we used to get as kids. Lots of components you can mix and match to make nearly anything. However, like a bare microcontroller, they usually don’t have much in the way of peripheral devices. So the secret sauce is what components you can surround the chip with.

If you are interested in retro computing, you ought to have a look at the ZX-Uno board. It hosts a Spartan 6 FPGA. They are for sale, but the design is open source and all the info is available if you prefer to roll your own or make modifications. You can see a video of the board in action, below (as explained in the video, the color issues are due to the capture card trying to deal with the non-standard sync rate).

Here are the key specifications:

  • FPGA Xilinx Spartan XC6SLX9-2TQG144C
  • Static Memory 512Kb, AS7C34096A-10TIN
  • 50MHz Oscillator
  • Video output (composite)
  • PS/2 keyboard
  • Stereo audio jack
  • EAR jack connector (for reading cassette tapes)
  • Connectors for JTAG and RGB
  • Slot for SD Cards
  • Expansion port with 3 male pin strips
  • Micro-USB power connector
  • PCB Size: 86×56 mm. (Compatible with Raspberry Pi cases)

In a recent post, we mentioned an Amstrad clone, and at least one commenter pointed out that the ZX Spectrum was more popular. However, with this board, you don’t have to choose. In the downloads section, there are bit streams (FPGA configurations) to let the board emulate several different computers, including several Commodore systems, some Atari systems, the BBC Micro, the ZX81, and more. Of course, the ZX Spectrum is at the top of the list.

If you decide to try one of these, you might need to brush up on your Spanish or keep a link to Google Translate handy. A lot of the surrounding community seems to be Spanish-speaking. But it looks like a nice board for doing any sort of computer platform you could cram into an FPGA.

If you want to learn ZX Spectrum assembly language (and who doesn’t?), we covered a good tutorial awhile back. It might take a USB to PS/2 adapter, but we’d love to see this board used with a keyboard like this one.

Thanks for the tip [Dave].

Filed under: classic hacks, FPGA

Custom Zynq/CMOS Camera Unlocks Astrophotography

Around here we love technology for its own sake. But we have to admit, most people are interested in applications–what can the technology do? Those people often have the best projects. After all, there’s only so many blinking LED projects you can look at before you want something more.

[Landingfield] is interested in astrophotography. He was dismayed at the cost of commercial camera sensors suitable for work like this, so he decided he would create his own. Although he started thinking about it a few years ago, he started earnestly in early 2016.

The project uses a Nikon sensor and a Xilinx Zynq CPU/FPGA. The idea is the set up and control the CMOS sensor with the CPU side of the Zynq chip, then receive and process the data from the sensor using the FPGA side before dumping it into memory and letting the CPU take over again. The project stalled for a bit due to a bug in the vendor’s tools. The posts describe the problem which might be handy if you are doing something similar. There’s still work to go, but the device has taken images that should appear on the same blog soon.

Along the way, the project shows you a lot about the interfaces between both the sensor and the FPGA, and the FPGA and the onboard ARM CPU. The writeups are way beyond a blink the light tutorial, but that’s a good thing if you have the will to dig through them. One interesting hack is that the build uses a 754 CPU socket to hold the image sensor.

We’ve looked at hacking film cameras to digital lately. If you prefer your telescopes in the cloud, there’s always the unfortunately named Skynet.

Filed under: ARM, digital cameras hacks, FPGA