I recently started FPGA programming and figured it would be fun to use an FPGA to implement the FizzBuzz algorithm. An FPGA (Field-Programmable Gate Array) is an interesting chip that you can program to implement arbitrary digital logic. This lets you build a complex digital circuit without wiring up individual gates and flip flops. It’s like having a custom chip that can be anything from a logic analyzer to a microprocessor to a video generator.
The “FizzBuzz test” is to write a program that prints the numbers from 1 to 100, except multiples of 3 are replaced with the word “Fizz”, multiples of 5 with “Buzz” and multiples of both with “FizzBuzz”. Since FizzBuzz can be implemented in a few lines of code, it is used as a programming interview question to weed out people who can’t program at all.
After a month of inactivity, I finally returned to my unfinished Yellowstone disk controller project to investigate the JTAG programming problems. Yellowstone is an FPGA-based disk controller card for the Apple II family, that aims to emulate a Liron disk controller or other models of vintage disk controller. It’s still a work in progress.
Last month I discovered some JTAG problems. With the Yellowstone card naked on my desk, and powered from an external 5V supply, JTAG programming works fine.
Steve Chamberlin over at Big Mess o’Wires has been working on an FPGA-based disk controller for Apple II, which he call Yellowstone:
Apple II disk controller cards are weird, there are a crazy number of different types, and many are rare and expensive. Can an FPGA-based solution save the day for retro collectors? You bet! Nearly all the existing disk controllers connect the same 8-bit bus to the same 19-pin disk interface, so a universal clone is merely a question of replacing the vintage 80s guts of the card with a modern reprogrammable FPGA. This hypothetical universal controller card could connect to almost any Apple II disk drive, or a Floppy Emu. Here’s my first attempt.
Black Mesa Labs is presenting an open-source-hardware USB 3.0 to FPGA PMOD interface design. First off, please lower your expectations. USB 3.0 physical layer is capable of 5 Gbps, or 640 MBytes/Sec. This project can’t provide that to your FPGA over 2 PMOD connectors – not even close. It does substantially improve PC to FPGA bandwidth however, 30x for Writes and 100x for Reads compared to a standard FTDI cable based on the FT232 ( ala RS232 like UART interface at 921,600 baud ). A standard FTDI cable is $20 and the FT600 chip is less than $10, so BML deemed it a project worth pursuing.
The BML 3bit HDMI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 using a 40 MHz dot clock. The TI TFP410 is very versatile in the resolutions it can generate and is really just limited by the clock that the FPGA can provide and the data rates the PMOD connectors are capable of.
Designing a power supply for FPGA includes multiple voltage, ripple management and power sequencing, here’s an app note from Maxim Integrated. Link here (PDF)
Field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) require 3 to 15, or even more, voltage rails. The logic fabric is usually at the latest process technology node that determines the core supply voltage. Configuration, housekeeping circuitry, various I/Os, serializer/deserializer (SerDes) transceivers, clock managers, and other functions all have differing requirements for voltage rails, sequencing/tracking, and voltage ripple limits. An engineer must consider all of these issues when designing a power supply for an FPGA.
Another application note from XJTAG on preparing Xilinx FPGA for proper boundary scan testing. Link here
When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing boundary scan testing to occur without any problems.
A second issue that can affect boundary scan testing with FPGAs is that they contain pull resistors. Depending on the design, these may be enabled when the FPGA is unconfigured as well as when it is configured. If these internal resistors are enabled on nets that contain pull resistors mounted on the board, two potential problems can occur:
1. If the internal resistor and external resistor pull in opposite directions, the boundary scan tests may not be able to test the external pull resistor if it is weaker than the internal pull resistor.
2. If the internal and external resistors pull in the same direction, a fault with the external resistor may not be detected because the internal resistor may mask the fault.
By setting the correct configuration options it is possible to disable these internal pull resistors when generating a ‘blank’ FPGA image.
Power down sequencing and discharging on FPGAs app note from Diodes Incorporated. Link here (PDF)
FPGA’s need the different power rails to be powered up and down in a defined sequence. For power down, each sequenced rail needs to be fully off before the next rail is turned off. With large high speed and high functionality FPGA’s, the power rails have large bulk capacitors to be discharged quickly and safely within a total time of 100ms and up to 10 rails each to be discharged within 10ms.
This application note shows a methodology and considerations for safe open ended shutdown to be controlled by a power sequencing circuit and using correctly chosen MOSFET to discharge the capacitor bank.
In this post you will find the description of a graphic display that uses a modular solution based on dot matrix blocks (in which each dot is a RGB LED), that are driven – via a specific bus – by a very powerful control board, that is entirely programmable and capable of managing even very fast animations, thanks to the FPGA it is supplied with. Yes, the key factor is the Spartan-6 Field Programmable Gate Array by Xilinx, that is able to execute programs at very high speed, thanks to its parallel processing capability (multi-thread); the model that has been used in the project was chosen because it represents the most performing FPGA available on the market as a TQFP package, therefore it may still be soldered by means of the traditional tools.