e2v’s application note interfacing their 1 Gsps 8-bit ADC to AVR. Link here (PDF)
With its smart feature (3-wire serial interface), e2v’s AT84AD001B dual 8-bit 1 Gsps ADC provides you with digital control over various functions offered with the dual ADC: calibration, gain and offset adjustments, DMUX ratio selection, analog and clock input mode, and partial or full standby mode.
This digital control via the 3-wire serial interface can be managed using Atmel’s ATmega128L AVR. The aim of this application note is to provide you with the relevant information for interfacing these two devices.
Clock jitter are a big issue in high-speed ADC, here’s an application note from e2V to guide users deals with these problems. Link here (PDF)
The e2v converters family addresses the high-speed market in the field of ADCs as well as DACs, with frequencies operating in the GHz range. Such high-speed devices require high-speed clock signals, which are usually subject to noise and wich users are not used to deal with. As a matter of fact, the clock signal integrity is one of the main factor to be taken into account for proper operation of an ADC.
High-speed ADCs require a low phase noise clock (namely a low jitter clock) in order to limit the dynamic performance degration caused by noise on the clock. Event though many manufacturers offer crystal oscillators with the right jitter characteristics, only a few are able to generate clocks in the GHz range.
These two issues are addressed in this paper, which intends to help the user understand the jitter phenomenon and design a proper clock with the right performance.
Another application note from e2v, this time about PCB design involving mixed-signal (Analog and Digital) components. Link here (PDF)
This application note aims at providing you with some recommendations to achieve improved performance.
The initial assumptions are the following:
• Proper grounding and routing of all signals is essential to ensure accurate signal conversion
• Eliminate the loop area return by using both separate ground plane and power plane
• Circuitry placement on mixed-signal PCBs is a crucial design point
In many cases, engineers have preconceived notions about mixed-signal designs and how analog and digital placement, partitioning and associated design should be performed.
When laying out components for a mixed-signal PCB, certain considerations are critical to achieve optimum performance. Mixed-signal is particularly tricky to design since analog devices possess different characteristics compared to digital components: different power rating, current, voltage and heat dissipation requirements, to name a few.
This study shows how to prevent digital logic ground currents from contaminating analog circuitry on a mixed-signal PCB and particularly ADC component. In our attempt to answer this question, let’s keep in mind two basic principles of electromagnetic compatibility. One is that currents should be returned to their source as locally and compactly as possible, through the smallest possible loop area. The second is that a system should have only one reference plane, if not we would create a dipole antenna.
e2V’s application note about dithering, adding noise to improve the dynamic range of ADCs. Link here (PDF)
High-speed ADCs today offer higher dynamic performances and every effort is made to push these state-of-the art performance through design improvements and also through innovative solutions at the system level.
For applications where the performance of the high-speed ADC in the frequency domain is the main critical parameter for the system overall performances, it is possible to improve the ADC response thanks to dither.
Dithering can be defined as adding some white noise, which has the effect of spreading low-level spectral components.
In this application note, the technique of dithering is presented, described and illustrated thanks to test results performed in the 10-bit 2.2Gsps ADC AT84AS008 device.