App note: An explanation of LCD viewing angle

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An application note from Hantronix, Inc. on LCD viewing angles and how it influences the selection of the right LCD for your application. Link here (PDF)

LCD displays have a limited viewing angle. They lose contrast and become hard to read at some viewing angles and they have more contrast and are easier to read at others. The size of the viewing angle is determined by several factors, primarily the type of LCD fluid and the duty cycle. Because the viewing angle tends to be smaller than most people would like, a bias is designed into the module at the time it is manufactured. This means the nominal viewing angle is offset from the perpendicular by some amount. Several versions of the LCD module are then offered with this bias set to different angles or positions to accommodate as many applications as possible. The term “bias angle” is often used erroneously with the term “viewing angle”.

App note: Designing with the EZ-USB FX3 Slave FIFO Interface

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Designing with the EZ-USB FX3 Slave FIFO Interface application note (PDF!) from Cypress:

AN65974 describes the synchronous Slave FIFO interface of EZ-USB FX3. The hardware interface and configuration settings for the FLAGs are described in detail with examples. The application note includes references to GPIF™ II Designer to make the Slave FIFO interface easy to design with. Two complete design examples are provided to demonstrate how you can use the synchronous Slave FIFO to interface an FPGA to FX3.

App note: MMCM and PLL dynamic reconfiguration

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Xilinx application note (PDF!) on MMCM and PLL dynamic reconfiguration:

This application note describes the information necessary to reconfigure the MMCM or PLL and provides a reference design that implements all of the algorithms covered. The PLL and MMCM share very similar functionality but are not identical. Due to some subtle functionality differences and the requirement for different settings, a separate PLL reference design is provided. To ensure correct operation, use the correct reference design for the clock management tile (CMT) being reconfigured.
Reconfiguration is performed through the DRP. The DRP provides access to the configuration bits that would normally only be initialized in the bitstream. This allows the user to dynamically change the MMCM or PLL clock outputs while the design is running. Frequency, phase, and duty cycle can all be changed dynamically. Fine-phase shifting is not allowed for the initial configuration or during reconfiguration.

App note: High-speed input clock issues

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Clock jitter are a big issue in high-speed ADC, here’s an application note from e2V to guide users deals with these problems. Link here (PDF)

The e2v converters family addresses the high-speed market in the field of ADCs as well as DACs, with frequencies operating in the GHz range. Such high-speed devices require high-speed clock signals, which are usually subject to noise and wich users are not used to deal with. As a matter of fact, the clock signal integrity is one of the main factor to be taken into account for proper operation of an ADC.

High-speed ADCs require a low phase noise clock (namely a low jitter clock) in order to limit the dynamic performance degration caused by noise on the clock. Event though many manufacturers offer crystal oscillators with the right jitter characteristics, only a few are able to generate clocks in the GHz range.

These two issues are addressed in this paper, which intends to help the user understand the jitter phenomenon and design a proper clock with the right performance.

App note: Power factor correction using the IRS2500

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Drop in replacement power factor correction chip IRS2500 from International Rectifier. Link here (PDF)

Many offline applications require power factor correction circuitry in order to minimize transmission line losses and stress on electrical generators and transformers created by high harmonic content and phase shift. Appliances often incorporate switching power supplies (SMPS) which include capacitive filter circuitry followed by a bridge rectifier and bulk capacitor supplying a load. Without power factor correction circuitry a SMPS draws a high peak current close to the line voltage peak and almost no current over much of the cycle, resulting in a power factor of around 0.5 and a high total harmonic distortion. Power factor correction circuitry is added which enables the appliance to draw a sinusoidal current from the AC line with negligible phase shift and very low harmonic distortion. This allows optimization of the load seen by the power grid such that power can be supplied without creating additional conductive losses in transmission lines or additional burden on transformers and generators. Costs to electricity providers are therefore reduced, which are hopefully passed on to the consumer.

App note: Low-Power Real Time Clock

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An application note (PDF!) on low-power real-time clock from Microchip:

This application note uses the Timer1 module, from a mid-range PIC16CXXX microcontroller, to control a low-power real-time clock. Timer1 was chosen because it has its own crystal which allows the module to operate during sleep. The two events that will wake the device from sleep (for this application) are a keypress and a Timer1 overflow.

App note: Auto-zero amplifiers ease the design of high-precision circuits

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An application note from Texas Instruments on new chopper amplifers superiority over old design chopper amps. Link here (PDF)

This article shows that the auto-zero calibration technique is very different from the chopper technique and is one that, when implemented through modern process technology, allows the economical manufacturing of wideband, high-precision amplifiers with low output noise.

App note: Transmitting SXGA video signal through 1kft (300m) CAT-5 cable

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An app note from Intersil on utilizing CAT-5 cable for SXGA video transimission. Link here (PDF)

The goal of this application note is to present the most current design methods for transmitting high bandwidth SXGA video signal over long distances of CAT-5 cable (300m or more). The enormous cost benefits of CAT-5 cable will also be discussed; for instance, the average cost of a 100m of CAT-5 cable is $20 while the average cost of a 100m of Coax Cable could easily exceed $240. Furthermore, wiring is reduced from a bulky hard to manage bundle of 3 cables to 1 easily pulled cable. Additionally, CAT-5 cable has a 4th twisted pair available, which can be used for KVM signal, audio, timing or control signal transmission.

App note: USB Mass storage class on an Embedded Host

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Microchip’s application note (PDF!) on USB Embedded Host Mass Storage class:

With the introduction of Microchip’s microcontrollers with the USB OTG peripheral, microcontroller applications can easily support USB Embedded Host functionality. One of the most common uses of this capability is to interface to mass storage devices, such as USB Flash Drives and memory card readers. These devices utilize the USB Mass Storage Class.

App note: Thermal behavior of small-signal discretes on multilayer PCBs

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App note from NXP Semiconductors about multilayer PCB as additional heatsink for flat SMD components mostly power transistors to dissipate heat. Link here (PDF)

This application note illustrates how to improve the power dissipation of discrete components by using multilayer PCBs. It focuses on the impact of using larger copper areas to improve the thermal behavior of applications.