For over the normal range temperature, Hantronix presents a simple temperature compensation circuit to correct LCD contrast, Link here (PDF)
The optimal contrast setting for LCD displays varies with ambient temperature. For most applications this variation in contrast is tolerable over the “normal” temperature range of 0°C to +50°C. Most Hantronix LCD modules are available with an extended temperature range option which allows the display to operate from -20°C to +70°C. The changes in contrast are NOT usually tolerable over this wide a range of temperatures, which means a way of adjusting the contrast voltage as the ambient temperature changes must be provided.
As the temperature decreases the LCD fluid requires a higher operating voltage in order to maintain a given optical contrast. One way to provide for this is to give the user control of the contrast. This is a simple solution but quite often its not desirable or practical.
Atmel’s application note (PDF!) Using the Master SPI Mode of the USART module:
• Enables Two SPI buses in one device
• Hardware buffered SPI communication
• Polled communication example
• Interrupt-controlled communication example
For the majority of applications, one Serial Peripheral Interface (SPI) module is enough. However, some applications might need more than one SPI module. This can be achieved using the Master SPI Mode of the devices with this feature such as Atmega48.
This application note (PDF!) from TI details the design of Single Phase PLL:
Grid connected applications require an accurate estimate of the grid angle to feed power synchronously tothe grid. This is achieved using a software phase locked loop (PLL). This application report discusses different challenges in the design of software phase locked loops and presents a methodology to design phase locked loops using C2000 controllers for single phase grid connection applications.
Another application note from Hantronix, Inc. on simple to digitally controlled efficient power supply for LCD display contrast. Link here (PDF)
Many LCD display modules require a negative or positive voltage that is higher than the logic voltage used to power an LCD. This voltage, called Vl, Vee or the bias voltage, would require a second power supply in the application device. If this power source is not available the LCD bias voltage must be generated from an existing voltage, either the logic voltage (+3.0-+5v) or a battery. This application note describes circuits for generating either a negative or positive LCD bias voltage from such a voltage source.
The LCD bias voltage is used to power the circuits that drive the LCD glass. This voltage sets the contrast level of the LCD. Since any changes in this voltage will cause a visible change in the contrast of the LCD it must be regulated to better than about 200mV. Any noise or ripple on this signal may cause visible artifacts on the LCD so they must be kept below about 100mV.
An application note from Hantronix, Inc. on LCD viewing angles and how it influences the selection of the right LCD for your application. Link here (PDF)
LCD displays have a limited viewing angle. They lose contrast and become hard to read at some viewing angles and they have more contrast and are easier to read at others. The size of the viewing angle is determined by several factors, primarily the type of LCD fluid and the duty cycle. Because the viewing angle tends to be smaller than most people would like, a bias is designed into the module at the time it is manufactured. This means the nominal viewing angle is offset from the perpendicular by some amount. Several versions of the LCD module are then offered with this bias set to different angles or positions to accommodate as many applications as possible. The term “bias angle” is often used erroneously with the term “viewing angle”.
Designing with the EZ-USB FX3 Slave FIFO Interface application note (PDF!) from Cypress:
AN65974 describes the synchronous Slave FIFO interface of EZ-USB FX3. The hardware interface and configuration settings for the FLAGs are described in detail with examples. The application note includes references to GPIF™ II Designer to make the Slave FIFO interface easy to design with. Two complete design examples are provided to demonstrate how you can use the synchronous Slave FIFO to interface an FPGA to FX3.
Xilinx application note (PDF!) on MMCM and PLL dynamic reconfiguration:
This application note describes the information necessary to reconfigure the MMCM or PLL and provides a reference design that implements all of the algorithms covered. The PLL and MMCM share very similar functionality but are not identical. Due to some subtle functionality differences and the requirement for different settings, a separate PLL reference design is provided. To ensure correct operation, use the correct reference design for the clock management tile (CMT) being reconfigured.
Reconfiguration is performed through the DRP. The DRP provides access to the configuration bits that would normally only be initialized in the bitstream. This allows the user to dynamically change the MMCM or PLL clock outputs while the design is running. Frequency, phase, and duty cycle can all be changed dynamically. Fine-phase shifting is not allowed for the initial configuration or during reconfiguration.
Clock jitter are a big issue in high-speed ADC, here’s an application note from e2V to guide users deals with these problems. Link here (PDF)
The e2v converters family addresses the high-speed market in the field of ADCs as well as DACs, with frequencies operating in the GHz range. Such high-speed devices require high-speed clock signals, which are usually subject to noise and wich users are not used to deal with. As a matter of fact, the clock signal integrity is one of the main factor to be taken into account for proper operation of an ADC.
High-speed ADCs require a low phase noise clock (namely a low jitter clock) in order to limit the dynamic performance degration caused by noise on the clock. Event though many manufacturers offer crystal oscillators with the right jitter characteristics, only a few are able to generate clocks in the GHz range.
These two issues are addressed in this paper, which intends to help the user understand the jitter phenomenon and design a proper clock with the right performance.
Drop in replacement power factor correction chip IRS2500 from International Rectifier. Link here (PDF)
Many offline applications require power factor correction circuitry in order to minimize transmission line losses and stress on electrical generators and transformers created by high harmonic content and phase shift. Appliances often incorporate switching power supplies (SMPS) which include capacitive filter circuitry followed by a bridge rectifier and bulk capacitor supplying a load. Without power factor correction circuitry a SMPS draws a high peak current close to the line voltage peak and almost no current over much of the cycle, resulting in a power factor of around 0.5 and a high total harmonic distortion. Power factor correction circuitry is added which enables the appliance to draw a sinusoidal current from the AC line with negligible phase shift and very low harmonic distortion. This allows optimization of the load seen by the power grid such that power can be supplied without creating additional conductive losses in transmission lines or additional burden on transformers and generators. Costs to electricity providers are therefore reduced, which are hopefully passed on to the consumer.
An application note (PDF!) on low-power real-time clock from Microchip:
This application note uses the Timer1 module, from a mid-range PIC16CXXX microcontroller, to control a low-power real-time clock. Timer1 was chosen because it has its own crystal which allows the module to operate during sleep. The two events that will wake the device from sleep (for this application) are a keypress and a Timer1 overflow.