LED signs and large LED video panels are always subjected to harsh environment resulting to corrosion to their pcb mountings, here’s an app note from OSRAM about potting these LED panels for protection. Link here (PDF)
This note provides basic information about the potting of flat SMT LEDs in video wall and signage applications. Thereby details on material in use, examples of suitable equipment and the process are presented and described. Additionally, the note gives a short intro into video walls with a typical setup, varying LED type system effects and general challenges. Finally, the results of selected environmental tests are presented, to demonstrate their impact and the aptitude of potting protection method.
New SMD LED design from OSRAM ideal for mounting on PCB holes for illumination. Link here (PDF)
This application note provides insight into the universally deployable and flexibly mountable light source of the PointLED® product family. A fundamental overview of the LED construction as well as the optical and electrical characteristics and performance of the LED are presented.
Proper handling of reed switches to prolong operation and or storage, an application note from HSI sensing. Link here (PDF)
Reed switches consist of two or three metal reed contacts (blades) that are hermetically sealed inside a glass tube. This seal, while strong, may be damaged if proper handling is not used. HSI Sensing has years of experience handling reed switches and have identified several best practices.
Another application note from e2v, this time about PCB design involving mixed-signal (Analog and Digital) components. Link here (PDF)
This application note aims at providing you with some recommendations to achieve improved performance.
The initial assumptions are the following:
• Proper grounding and routing of all signals is essential to ensure accurate signal conversion
• Eliminate the loop area return by using both separate ground plane and power plane
• Circuitry placement on mixed-signal PCBs is a crucial design point
In many cases, engineers have preconceived notions about mixed-signal designs and how analog and digital placement, partitioning and associated design should be performed.
When laying out components for a mixed-signal PCB, certain considerations are critical to achieve optimum performance. Mixed-signal is particularly tricky to design since analog devices possess different characteristics compared to digital components: different power rating, current, voltage and heat dissipation requirements, to name a few.
This study shows how to prevent digital logic ground currents from contaminating analog circuitry on a mixed-signal PCB and particularly ADC component. In our attempt to answer this question, let’s keep in mind two basic principles of electromagnetic compatibility. One is that currents should be returned to their source as locally and compactly as possible, through the smallest possible loop area. The second is that a system should have only one reference plane, if not we would create a dipole antenna.
e2V’s application note about dithering, adding noise to improve the dynamic range of ADCs. Link here (PDF)
High-speed ADCs today offer higher dynamic performances and every effort is made to push these state-of-the art performance through design improvements and also through innovative solutions at the system level.
For applications where the performance of the high-speed ADC in the frequency domain is the main critical parameter for the system overall performances, it is possible to improve the ADC response thanks to dither.
Dithering can be defined as adding some white noise, which has the effect of spreading low-level spectral components.
In this application note, the technique of dithering is presented, described and illustrated thanks to test results performed in the 10-bit 2.2Gsps ADC AT84AS008 device.
App note from Vishay on high-side MOSFET failures investigation leads to one of the following modes of operation:
(a) High-impedance gate drive
(b) Electro-static discharge (ESD) exposure
(c) Electrical over-stressed (EOS) operation
More on it here (PDF)
Power MOSFET failures in high-side applications can often be attributed to a high-impedance gate drive creating a virtual floating gate, which in turn increases the susceptibility of the MOSFET to failure during system-generated ESD and EOS scenarios.
More to know about MOSFET gate threshold voltages, an application note from Vishay. Link here (PDF)
The question of how to turn on a MOSFET might sound trivial, since ease of switching is a major advantage of field-effect transistors. Unlike bipolar junction transistors, these are majority carrier devices. One does not have to worry about current gain, tailoring the base current to match the extremes of hfe and variable collector currents, or providing negative drives. Since MOSFETs are voltage driven, many users assume that they will turn on when a voltage, equal to or greater than the threshold, is applied to the gate. However, the question of how to turn on a MOSFET or, at a more basic level, what is the minimum voltage that should be applied to the gate, needs reappraisal with more and more converters being controlled digitally. While digital control offers the next level of flexibility and functionality, the DSPs, FPGAs, and other programmable devices with which it is implemented are designed to operate with low supply voltages. It is necessary to boost the final PWM signal to the level required by the MOSFET gate. This is where things begin to go wrong, because of the misconceptions about what really turns on a MOSFET. Many digital designers look at the gate threshold voltage and jump to the conclusion that, just as with their digital logic, the MOSFET will change state as soon as the threshold is crossed.