App note: Parallel configuration of H-bridges featuring the MC33932 and MC34932 ICs

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Old application note from ON Semiconductors on getting increased power capability by paralleling H-bridges and overcoming current limit imbalance between the two drivers by properly designing the board layout. Link here (PDF)

Two or more H-bridges can be operated in parallel to increase the current handling capacity of the circuit. In this application note, paralleling of H-bridges has been exemplified using a dual H-bridge model MC33932/MC34932. However, paralleling of H-bridges is not an easy task, as any offset or mismatch between the two MOSFETs can cause one of them to hit the over current/temperature limit before the other, forcing very high-current through one of the H-bridges in parallel configuration, which may initiate device shutdown.

The objective of this application note is to present a method to obtain twice the current from a dual H-bridge by paralleling the dual H-bridges located on the same die. This document also presents the various methods to calculate the junction temperature, to ensure the device operates within the thermal limits specified in the data sheet.

App note: Duty cycle and power optimization

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Power saving specially on battery operated devices need to be kept, in this application note from ON Semiconductors discussed how to keep duty cycle in which a wireless RF device is operated at a minimum time. Link here (PDF)

Consider a battery powered device (target), which should receive data from a second device (initiator) from time to time. To reduce power consumption, the target switches its receiver on for only a short while, checking if there is any RF activity, and returns to sleep if there is no data to receive.

The ratio of the time ton during which the target is powered on, to the time toff during which the target is powered off is called duty cycle. If for example the target is powered off for 1 second, powered on for 1 millisecond, powered off for 1 second and so on, its duty cycle is 1:1000.

App note: Rectifiers for Power Factor Correction

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Another Vishay’s app note about power factor correction this time about the component used and their effects. Link here (PDF)

PFC devices are generally selected base on the speed of their reverse recovery time (trr). Currently for CCM (Continuous-Conduction-Mode) and CRM (Critical Conduction-Mode) PFC devices in market, rectifiers up to 600 V with trr smaller or equal to 35 ns are generally used as CCM PFC; rectifiers up to 600 V with reverse recovery time between 35 ns to 60 ns are used as CRM PFC.

It should be noted there is a tradeoff between forward voltage drops and switching speed; when the reverse recovery time of Ultrafast rectifiers are less than 35 ns, their forward voltage drops would increase significantly, in turn the devices’ forward surge current abilities would be diminished, therefore cautious attention should be taken when selecting the appropriate CCM or CRM PFC devices for various switch mode power supply applications, such that expected performance could be achieved and better reliability would still be ensured.

App note: Power factor correction with ultrafast diodes

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Vishay’s app note in keeping the power supplies’ power factor in check with their ultrafast diodes. Link here (PDF)

More and more switched mode power supplies (SMPS) are being designed with an active power factor correction (PFC) input stage. This is mainly due to the introduction of regulations aimed at restricting the harmonic content of the load current drawn from power lines. However, both the user and the power company benefit from PFC, so it just makes good sense.

App note: Limiting inrush current

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Aimtec’s app note on inrush current on power converters and their solution. Link here

Inrush currents can be problematic in circuits that utilize overload protection devices such as fuses and circuit breakers. The selection of overcurrent protection devices is made more complicated when high inrush currents are present. False overload conditions can trigger unwanted protection events.

App note: Forced air convection and heat sinking for power supplies

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Application note from Aimtec discusses about two ways for taking away heat on power supplies. Link here

When evaluating the operating temperature ranges of power supplies one must consult component’s datasheets. Datasheets state a “usable” operating temperature range typically given at full output load. In order to reach the upper limit of the temperature ranges without derating the load, some additional heat dissipation may be required.

App note: Method to reduce the output ripple & noise of power supplies

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Another app note from Aimtec on power supplies and how to minimize their output noises. Link here

The switching power supplies have the fundamental advantage of high efficiency i.e. low power dissipation when compared to linear voltage regulation. However, there exists an important consideration concerning the presence of ripple and noise at their outputs. If the ripple and noise are left unfiltered their levels may be sufficiently high to adversely affect other devices connected to the same power supply. Fortunately there exists methods to cost effectively reduce the impact of ripple and noise.

App note: Best design and layout practices for SiTime oscillators

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SiTime’s app note about how to properly route an oscillator’s PCB traces. Link here

Proper decoupling, bypassing, and power supply noise reduction is important in many applications to ensure optimal performance for oscillators. A common strategy is to place capacitors near high speed devices on a printed circuit board (PCB). These capacitors serve important functions:
– Provide instantaneous current to the component
– Reduce noise propagation through the system
– Shunt the power supply noise to GND
The following sections describe decoupling, bypassing, noise rejection, and power supply condition recommendations for SiTime’s single-ended and differential timing devices.