– Fits ESP-12 and ESP-07 module
– Single-sided self-etchable design
– Few, cheap parts in SMD
– Breadboard-style – one row on each side accessible
– Vin >4.5V (max. 7V) input possible with 3V3 onboard voltage regulator (with two capacitors 10µF)
– Power-indicator LED
– (Schottky-) Diode as reverse polarity input protection possible (solder 0 Ohm resistor or just connect the two pads for no protection)
-RST, CH_PD, GPIO0 with 4k7 pull-up resistors on board (resistors can be omitted if remote access of those GPIOs is needed)
– GPIO15 with 4k7 pull-down (see above)
– Tactile switch connected to GPIO0 to get into flash mode
– Single post for 3.3V output near voltage regulator
This is a second article related to Mullard 3-3 Amplifier Project and in this article we introduce HT transformer and HT power supply related to this amplifier. As mentioned in previous post, power supply unit of this tube amplifier is constructed using 400V 5A bridge rectifier, 220µF (400V) and 82µF (400V) electrolytic capacitors.
The most vital component of this power supply is HT transformer and due to limited availability we construct this transformer by ourselves.
Given the popularity of the 555 timer, I thought it would be interesting to find out what’s inside the 555 timer and how it works. While the 555 timer is usually sold as a black plastic IC, it is also available in a metal can, which can be cut open with a hacksaw revealing the tiny die inside.
Another application note from Hantronix, Inc. on simple to digitally controlled efficient power supply for LCD display contrast. Link here (PDF)
Many LCD display modules require a negative or positive voltage that is higher than the logic voltage used to power an LCD. This voltage, called Vl, Vee or the bias voltage, would require a second power supply in the application device. If this power source is not available the LCD bias voltage must be generated from an existing voltage, either the logic voltage (+3.0-+5v) or a battery. This application note describes circuits for generating either a negative or positive LCD bias voltage from such a voltage source.
The LCD bias voltage is used to power the circuits that drive the LCD glass. This voltage sets the contrast level of the LCD. Since any changes in this voltage will cause a visible change in the contrast of the LCD it must be regulated to better than about 200mV. Any noise or ripple on this signal may cause visible artifacts on the LCD so they must be kept below about 100mV.
An application note from Hantronix, Inc. on LCD viewing angles and how it influences the selection of the right LCD for your application. Link here (PDF)
LCD displays have a limited viewing angle. They lose contrast and become hard to read at some viewing angles and they have more contrast and are easier to read at others. The size of the viewing angle is determined by several factors, primarily the type of LCD fluid and the duty cycle. Because the viewing angle tends to be smaller than most people would like, a bias is designed into the module at the time it is manufactured. This means the nominal viewing angle is offset from the perpendicular by some amount. Several versions of the LCD module are then offered with this bias set to different angles or positions to accommodate as many applications as possible. The term “bias angle” is often used erroneously with the term “viewing angle”.
Designing with the EZ-USB FX3 Slave FIFO Interface application note (PDF!) from Cypress:
AN65974 describes the synchronous Slave FIFO interface of EZ-USB FX3. The hardware interface and configuration settings for the FLAGs are described in detail with examples. The application note includes references to GPIF™ II Designer to make the Slave FIFO interface easy to design with. Two complete design examples are provided to demonstrate how you can use the synchronous Slave FIFO to interface an FPGA to FX3.
This application note describes the information necessary to reconfigure the MMCM or PLL and provides a reference design that implements all of the algorithms covered. The PLL and MMCM share very similar functionality but are not identical. Due to some subtle functionality differences and the requirement for different settings, a separate PLL reference design is provided. To ensure correct operation, use the correct reference design for the clock management tile (CMT) being reconfigured.
Reconfiguration is performed through the DRP. The DRP provides access to the configuration bits that would normally only be initialized in the bitstream. This allows the user to dynamically change the MMCM or PLL clock outputs while the design is running. Frequency, phase, and duty cycle can all be changed dynamically. Fine-phase shifting is not allowed for the initial configuration or during reconfiguration.
When S/PDIF became available in the Teensy Audio Library I thought this might be the solution to ground loop problems I’d been having when interfacing projects to my PC. However, I quickly realized I didn’t have any sound cards with an S/PDIF interface.
In the belief that I’d rather build than buy I decided to update one of my previous projects, a PCM2904 based sound card, to include an S/PDIF interface.
OpenDrop is a new design for an open source digital microfludics platform for research purposes. The device uses recent electro-wetting technology to control small droplets of liquids. Potential applications are lab on a chip devices for automating processes of digital biology. How ever the present design should also open the technology to other field and allow experimentation to find new applications. Including the field of art, music, games and education.