How can you count bits in hardware? In this article, I reverse-engineer the circuit used by the ARM1 processor to count the number of set bits in a 16-bit field, showing how individual transistors form multiplexers, which are combined into adders, and finally form the bit counter. The ARM1 is the ancestor of the processor in most cell phones, so you may have a descendent of this circuit in your pocket.
Mullard 3-3 is quiet popular 3W tube amplifier introduced by Mullard Ltd in 1956. A schematic and design detail of this amplifier is available in “Mullard Circuits for Audio Amplifiers” book and in National Valve Museum article. This amplifier is based on EF86, EL84 vacuum tubes and EZ80 full wave rectifier tube. In this project we decided to construct this original Mullard 3-3 Amplifier with some slight changes and commonly available electronic components.
In our prototype we replace EZ80 tube with 400V 5A bridge rectifier which is commonly available in many electronic spare parts shops. Also we replace EL84 with 6P14P pentode and EF86 with 6J8 pentode. Both of these valves can directly use with this circuit and those values are available for lesser price than EL84, EF86 tubes.
In this blog post, I will show you how to build a 0 to 5.8 GHz tracking generator for the HP 8566B 100 Hz to 22 GHz spectrum analyzer using off-the-shelf components for under $100. Although this tracking generator is specifically designed for my HP 8566B spectrum analyzer, the method discussed below is applicable to pretty much any spectrum analyzer that has an LO output (typically the 1st LO).
A tracking generator, as its name implies, tracks the frequency of the spectrum analyzer’s sweeping oscillator (typically 1st LO) so that the tracking generator’s frequency output matches the center frequency of the bandpass filter in spectrum analyzer’s IF stage. Thus at any given moment, the spectrum analyzer sees the same frequency input as what it is currently sweeping at. The combination of a spectrum analyzer and a tracking generator is often referred to as a scalar network analyzer (SNA).
This was a project begun last winter in the hopes of having an array of thermocouples to monitor my old woodstove when operating it. Well, I never got around to finishing it, but I have a fancy new woodstove as of this fall, and I would love to monitor its temperature curves likewise!
This BoosterPack is fancied as a baseboard plugging underneath the LaunchPad, with four holes for mounting studs in case I ever decide to fix it inside a permanent enclosure (probably one made of aluminum due to the heat). I could have pushed the Thermocouple terminal blocks out a little further to fit more launchpads, as I feel this is a bit tight. I chose a Tiva-C LP for my pics because it fits nicely but the BoosterPack is designed with low-power features, contrary to the MAX31855’s own design.
Almost every smartphone uses a processor based on the ARM1 chip created in 1985. The Visual ARM1 simulator shows what happens inside the ARM1 chip as it runs; the result (below) is fascinating but mysterious. In this article, I reverse engineer key parts of the chip and explain how they work, bridging the gap between the puzzling flashing lines in the simulator and what the chip is actually doing. I describethe overall structure of the chip and then descend to the individual transistors, showing how they are built out of silicon and work together to store and process data. After reading this article, you can look at the chip’s circuits and understand the data they store.
Another application note from e2v, this time about PCB design involving mixed-signal (Analog and Digital) components. Link here (PDF)
This application note aims at providing you with some recommendations to achieve improved performance.
The initial assumptions are the following:
• Proper grounding and routing of all signals is essential to ensure accurate signal conversion
• Eliminate the loop area return by using both separate ground plane and power plane
• Circuitry placement on mixed-signal PCBs is a crucial design point
In many cases, engineers have preconceived notions about mixed-signal designs and how analog and digital placement, partitioning and associated design should be performed.
When laying out components for a mixed-signal PCB, certain considerations are critical to achieve optimum performance. Mixed-signal is particularly tricky to design since analog devices possess different characteristics compared to digital components: different power rating, current, voltage and heat dissipation requirements, to name a few.
This study shows how to prevent digital logic ground currents from contaminating analog circuitry on a mixed-signal PCB and particularly ADC component. In our attempt to answer this question, let’s keep in mind two basic principles of electromagnetic compatibility. One is that currents should be returned to their source as locally and compactly as possible, through the smallest possible loop area. The second is that a system should have only one reference plane, if not we would create a dipole antenna.
e2V’s application note about dithering, adding noise to improve the dynamic range of ADCs. Link here (PDF)
High-speed ADCs today offer higher dynamic performances and every effort is made to push these state-of-the art performance through design improvements and also through innovative solutions at the system level.
For applications where the performance of the high-speed ADC in the frequency domain is the main critical parameter for the system overall performances, it is possible to improve the ADC response thanks to dither.
Dithering can be defined as adding some white noise, which has the effect of spreading low-level spectral components.
In this application note, the technique of dithering is presented, described and illustrated thanks to test results performed in the 10-bit 2.2Gsps ADC AT84AS008 device.
App note from Vishay on high-side MOSFET failures investigation leads to one of the following modes of operation:
(a) High-impedance gate drive
(b) Electro-static discharge (ESD) exposure
(c) Electrical over-stressed (EOS) operation
Power MOSFET failures in high-side applications can often be attributed to a high-impedance gate drive creating a virtual floating gate, which in turn increases the susceptibility of the MOSFET to failure during system-generated ESD and EOS scenarios.